The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process is the result of various process changes and improvements, including more precise lithography. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
As components become smaller and patterning techniques become more precise, the topography of the substrate on which the components are fabricated becomes more important. For example, if the topography of a semiconductor wafer becomes non-planar, or complicated, the result can have a negative impact on alignment performance of a lithography exposing tool. Further, the result can have a negative impact on an overlay of a resist pattern to a material feature embedded in the semiconductor wafer. Accordingly, what is needed is a method for improving a patterning process used to expose a substrate such as a semiconductor wafer.